Dr. Babak Rahbaran

Babak Rahbaran is working since 2010 at the Austrian Academy of Science as Technical Project leader where he is leading the "CMS (compact Muon Solenoid) trigger electronic" group for the Global Trigger project at LHC (Large Hadron Collider) accelerator at CERN in Geneva. The CMS trigger system reduces the input rate of up to 1 GHz of proton collisions at Level 1 with dedicated hardware to 100 kHz and then with the Higher Level Triggers (HLT) running on a computer farm to 100 -300 Hz for writing to tape. The Global Trigger system makes the actual decisions on which beam crossings are accepted by collecting data from the calorimeter and 3 muon trigger systems every 25 ns. The Global Trigger system also orchestrates the synchronization of the readout and trigger subsystems. He has the responsibility for the technical functioning of this system. He and his team are responsible for the operation of this system, its maintenance and development and its adaptation to the frequent changes in experimental conditions. The successful discovery of the Higgs particle is evidence for the successful operation of the trigger system. Additionally he meets the extraordinary challenge of bringing online more than a dozen new trigger menus as the LHC luminosity climbed from startup almost 6 orders of magnitude to exceed the LHC design interaction pile-up conditions. The successful discovery of the Higgs particle is evidence for the successful operation of the trigger system.

He offered consulting in the area of specialized electronics development for devices such as FPGA, ASIC. He is experienced in designing and implementing safe and robust software architecture for autonomous applications. Before that he worked as Project Leader at Semantic Supercomputing sub-division of Science Division, Senior FPGA Application Designer at Austrian Institute of Technology-AIT), Assistant Professor at the Institute for Computer Engineering (Vienna University of Technology) as Course Directors for “Digital Design Laboratory” for Computer Science Study for 120 students per year and scientific assistant at the Institute for Computer Engineering-Embedded Computer Systems Group (Vienna University of Technology). In the last decade, he has been involved in many industrial and scientific projects concerned with real-time communication networks, the design of fault-tolerant computer architectures and their evaluation by means of fault-injection, design/implementation of Information Retrieval application for FPGA High Performance computing.

His current activity is focusing on new state-of-the art link system is a first implementation of technologies to be used for the trigger upgrade and by his work on this he  is helped to lead the way to the trigger upgrade using the latest telecom link and fiber optic technologies. He plays a leading role in the upgrade of the Global Trigger for the higher luminosity LHC running. This is scheduled for operation in 2016.

Educations

PhD      Computer Engineering at Vienna University of Technology, (PhD), with highest distinction,
http://doi.ieeecomputersociety.org/10.1109/TDSC.2008.37

M.Sc     Electrical Engineering; Computer Science at Vienna University of Technology, Diplom-Ingenieur (M.Sc.)

Employment Record

Multi-Project Leading for CERN (European Organization for Nuclear Research) project:

2010-now    Technical Project Leader for the Project ,Global Trigger Upgrade‘ for the LHC (Large Hadron Collider) ,Compact Muon Solenoid‘, CMS (http://cms.web.cern.ch/)

2010-now    Technical Project Leader for the Project ,Global Trigger‘ for the LHC (Large Hadron Collider) ,Compact Muon Solenoid‘ (CMS ) (http://cms.web.cern.ch/)

2012-now    Teaching at Vienna University of Technology, 182.726 FPGA-Design -- Refinement Vienna University of Technology, ECTS 3.0, Typ: VU Lecture and exercise https://tiss.tuwien.ac.at/course/courseDetails.xhtml?locale=de&windowId=acb&courseNr=182726&semester=2012S

2006-2010    Project leader — Senior FPGA Design Application Engineer for “High Performance Computing” Platform in domain „Patent Retrieval (Patent search)“ and  „Data Mining“  Science Division, Semantic Supercomputing sub-division

2005-2006    Senior FPGA Application Designer, ARC Seibersdorf research GmBH, domain Information technique

1999–2005   Course Directors— Assistant Professor, Institute of Computer Engineering, Embedded Computing Systems Group, Vienna University of Technology

Research project: A Fault-Tolerance Layer for a Distributed Real-Time System

Responsibility

• Lead the engineering team in the electronics, firmware as well as software design for use as trigger electronic for CMS detector of LHC


• Technical Leadership of Global Trigger (GT) and Global Trigger Upgrade (µGT) projects @CERN/Vienna


• Plan the engineering development: Hardware, Firmware, Software


• Breakdown development into work packages


• Estimate effort associated with work packages


• Tailor development process to project needs


• Direct week-to-week activities of an engineering development team, including electrical, software and validation engineers


• Prioritize engineering resources


• Act as the primary technical interface to the customer (High Energy Physic physicists of 5 countries)


• Manage engineering risks. Elevate risks soon enough to apply corrective action.


• Report status, prepare contingency plans and execute corrective actions.


• Manage changes: Estimate cost and timing impact of change requests, negotiate implementation with customer


• Assisting customer engineering teams with presentation of design concepts and evidence of design objectives being met


• Ongoing maintenance / development of the existing and ongoing CMS trigger systems with my Team in Vienna and CERN


• Upgrade of trigger electronics (using MicroTCA as a platform) based on Virtex-7


• Design, implementation and validation of a system appropriate for the trigger upgrade using a µTCA platform based on Virtex-7 (XC7VX690T)


• 750Gb/s in and 750Gb/s outbandwidth implementation

Publications

Author and co-author of over 400 Publication of CMS-Experiment

Selected Publications

Categories: T Thesis, J Journal, P Conference Proceedings, O Oral Presentations, R Technical Report,

                   H   High Energy Physics

J     2015    Babak Rahbaran, Global Trigger Upgrade firmware architecture for the level-1 Trigger of the  CMS experiment

H    2013   Observation of a new boson with mass near 125 GeV in pp collisions at  sqrt(s) = 7 and 8 TeV   (20.06.2013)

H   2013   Search for supersymmetry in final states with a single lepton, b-quark jetsand missing  transverse energy in proton-proton collisions at sqrt(s) = 7 TeV

H   2013    Measurement of the Y(1S), Y(2S) and Y(3S) polarizations in pp collisions at sqrt(s) = 7 TeV

H   2012     Observation of a New Xi_b Baryon

H   2012     Inclusive b-jet production in pp collisions at sqrt(s)=7TeV

H   2011    Search for supersymmetry in pp collisions at sqrt(s)=7 TeV in events with a single lepton, jets,  and missing transverse momentum

J     2011     Babak Rahbaran, MicroTCA-based Global Trigger Upgrade project for the CMS experiment at LHC, IOP Science, Journal of Instrumentation,  http://iopscience.iop.org/1748-0221/6/12/C12054/
J     2004     Babak Rahbaran, Matthias Fuegger and Andreas Steininger. Embedded Real-Time- Tracer--An Approach with IDE. Telematik Magazine, 2004
J     2008     Babak Rahbaran and Andreas Steininger. Is asynchronous logic more robust than synchronous logic? IEEE Transactions on Dependable and Secure Computing, October-December 2009 (vol. 6 no. 4), pp. 282-294
O     2002     B. Rahbaran, and A. Steininger. An FPGA-Based Development Platform for the Virtual Real-Time Processor Component SPEAR. In Proceeding of IEEE Design and Diagnostics of Electronic circuit and Systems Workshop-DDECS, pages 98-105. Brno, Czech Republic, 2002.
O     2003     A. Steininger, B. Rahbaran, and T. Handl. Built-in Fault Injectors-The Logical Continuation of BIST?  In First Workshop on Intelligent Solutions in Embedded systems,WISES03. Vienna University of Technology, Austria, 2003
O     2004     Babak Rahbaran, Andreas Steininger, and Thomas Handl. Built-in fault injection in hardware - the FIDYCO example. Electronic Design, Test and Applications, IEEE International Workshop on Electronic Design, Test and Applications- Delta 2004, Perth Australia, pages 327-332, 2004.
O     2004     Babak Rahbaran and Andreas Steininger. Real-time Fault Injection with the Signal-Flip model by FIDYCO. The International Conference on Dependable Systems and Networks-DSN-2004, Jun. 2004.
O     2004     Use of Hardware fault-injection in FPGA with special focus on Transient Fault, Special Lecture for Company Robert Bosch (Stuttgart)
 
P     2001     M. Delvai, W. Huber, B. Rahbaran, and A. Steininger. SPEAR-Design-Entscheidung für den Scalable Processor for Embedded Application in Real-Time Environments. In Austrochip 2001 Tagungsband.
P     2004     Babak Rahbaran, Matthias Fuegger, and Andreas Steininger. Embedded Real-Time-Tracer--An Approach with IDE. In Proceedings of the Second Workshop on Intelligent Solutions in Embedded Systems,WISES2004, pages 25-36, 25 June 2004.
R     2003     B. Rahbaran. Die wichtigsten kommandos in der dc shell. Technical report, Vienna University of Technology, Embeded Computing System Group, 2003.
R     2004     Babak Rahbaran. The Concept of synchronous and asynchronous Golden Run for FIDYCO. Technical report, Vienna University of Technology-Embedded Computing System, September 2004.
R     2004     Babak Rahbaran. The Concept of USB NOLOSS Interface for FIDYCO. Technical report, Vienna University of Technology-Embedded Computing System, Mai 2004.
R     2004     Babak Rahbaran. Performing Automatic Physical Injection of Signal-Flips and Delay Faults with the toolset FIDYCO. Technische Universität Wien, Institut für Technische Informatik, Treitlstr. 1-3/182-1, 1040 Vienna, Austria, 2004.
R     2004     Babak Rahbaran. VHDL Design Hierarchy Signal ManipulatorVDHSM. Technical report, Vienna University of Technology-Embedded Computing System, September 2004.
R     2004     Babak Rahbaran and Andreas Steininger. A Strategy for Experimental Fault Injection into an Asynchronous Processor. Research Report 98/2004, Technische Universität Wien, Institut für Technische Informatik, Treitlstr. 1-3/182-1, 1040 Vienna, Austria, 2004.
T     1991     Babak Rahbaran, B.Sc. Thesis, Development of Robot arm system with six degrees of freedoms, Tehran University, Iran, 1991
T     1998     B. Rahbaran. Analyse und Entwurf unterschiedlicher LDC host-interfaces. Master's thesis, Vienna University of Technlogy, Austria,1998
T     2005     B. Rahbaran. An Experimental Comparison of Robustness between Synchronous and Asynchronous Logic Design. PhD thesis, Vienna University of Technology, Austria